I have uploaded a video to YouTube which gives an overview of this card as well as a slightly more detailed description of the ROM/RAM switch-over circuit:
This design supersedes the revision 1 design of the SBC, this revision is fully backwards compatible with software designed for revision 1, with the exception of any that require I/O port $00 for it’s operation.
Changes since Rev 1
- Changed the UART (16C550) package from DIP40 to PLCC44, this reduces the size and is easier to source.
- Bank 0 and 1 are now hardwired to be ROM/RAM for Bank 0, and RAM for Bank 1 (the Bank 1 is the 16K upper half of the RAM chip).
- Circuitry has been added to exchange the ROM in Bank 0 for the 16K lower half of the RAM chip.
- Header for Bluetooth module removed, this can be still used by making a cable to attach to the FTDI cable header.
- All discrete components are now through hole to make it easier for people to build.
- USB socket for power removed, power can be fed in via the FTDI cable or the M62 bus still.
- correct shape is now cut either side of the edge connector
Bank_0 ROM/RAM switching logic
The SBC Rev 2 now incorporates a circuit to allow the Bank_0 to be switched between 16K of ROM or the lower 16K of the RAM chip. The upper 16K of the RAM chips is permanently assigned to Bank_1.
I have implemented this to work towards porting CP/M to the M62 system eventually. I also use this in the OS I am currently developing.
Switching between the ROM and RAM is done by writing to I/O port $00, writing $00 will select ROM mode, and $01 will select RAM mode. This circuit will automatically switch back to ROM mode when RESET is asserted, this ensures that the ROM is always available during a cold boot of the SBC.
(Logic Circuit is a free logic simulation tool that I was introduced to at university, I use it to check all my logic before I implement them in my circuits)
The schematic PDF of the SBC rev 2 can be downloaded here
- The ROM/RAM switch-over circuit is actually mapped to I/O ports $00 to $07 instead of just $00 as originally intended.
- The UART socket wasn’t measured correctly and slightly encroaches into the space of some caps and another chip socket.
Changes to be considered for the next revision:
- Better spacing of the chip sockets.
- Using a PLC package version of the Z80 instead of the DIP to save space.
- Add an extra decoder chip to the I/O address decoding so the ROM/RAM switch-over circuit can just go to $00 as intended
- Add a latch to the NMI input that can be reset via I/O so re-triggering of NMI can be disabled until the Z80 is ready to allow it. At current, the Z80 can enter the NMI vector when NMI is triggered and then re-enter if it gets re-triggered before it’s finished doing it’s NMI stuff.
- Possibly a surface mount version of the SBC (ROM,Z80, and UART will remain in sockets).