I am slowly developing a VGA interface for the M62 project, unfortunately lack of time and experience with Verilog/VHDL is causing this to progress at a very slow pace. It is currently at the stage of generating some rudimentary sync signals.
Proposed block diagram
(note some blocks may or may not be with the programmable logic)
The minimum functionality that I hope to achieve is a text display interface which allows me to write ASCII characters to the interface and they are written into the VRAM and then displayed.
The best scenario would be a full graphics interface which I can send draw commands via the interface or raw bitmap data.
A secondary goal of this interface is to have a PS/2 Keyboard interface to allow keyboard input as companion to the video output allowing the computer to be independent of another computer acting as a terminal.
The interface should handle all data/command transactions with the host system and negotiate the updating of the VRAM during the VGA retrace period, this would avoid having to make the host synchronize itself with the VGA refresh timing as older systems tend to do.
The VGA Core itself is responsible for generating the VGA Sync signals and translating the VRAM to the VGA display and display characters using the character ROM accordingly. It will let the interface know when it is in retrace period, so it can have the VRAM updated if needed.
The DAC can be as many bits wide as VRAM can accommodate, a single resistor passthrough allowing 1 bit per colour will allow 8 colours which is perfectly fine for a basic display.
The VRAM can either be within the programmable logic or external depending on the requirements.
The Character ROM should contain the standard characters required to allow all printable ASCII characters.
Having a PS/2 interface on the VGA interface card will allow us to have both input and output on the same card. I propose that the PS/2 interface be part of the interface block with a LIFO buffer that the keypresses are inserted, allowing the host read any backlog of keypresses when it is ready. Polling of a status register can indicate if there are keypresses available, and a read from a keyboard register would remove the oldest entry in the LIFO buffer and send it to the host.
I would prefer to use an inexpensive CPLD/FPGA that does not require an external configuration ROM.
Using a Xilinx XC9572 would be nice as I have a couple of those at hand and they seems to be cheap enough to get as they are around $6-$7 on digikey.
Other CPLDs should be fine if they are easily accessible and are inexpensive. I personally only have development tools for Xilinx and Altera devices.
This interface is intended to be used on a 5V TTL level bus and would ideally conform with the M62 card specifications (see physical specifications section).
Anyone wish to help with this?
If anyone who is proficient in VHDL or Verilog is interested in helping with building the core of the interface, the project would benefit greatly. The specifications I am developing creates an open interface that can be used on many other platforms, not just the M62.
If you have a similar interface that you think would work for this project please let me know, if you are interested in providing the schematics/source so it could be integrated or adapted that would be excellent, or if you wish to keep your interface closed and provide specifications to talk to it and purchase each interface from you, that would work too.
Any provided information/help will always be fully attributed and credited to the author/s
Should you wish to help in any way with this, please contact me via the donations page. Many thanks.