M62 – Z80 SBC Card – Rev 3


Details of this revision:

  • Backwards compatible with Rev 1 and 2.
  • Almost everything is surface mount, this reduces the size.
  • We now have a Compact Flash socket included on the board.
  • There is an optional isolated USB-UART interface based on the CH340G (I did notice I made a mistake in the silkscreen)
  • We have 512KB each of ROM and RAM (Paged through Bank 0, more on that later)
  • You can select an external clock for the Z80, the 4MHz remains connected to the M62 bus and the on-board UART
  • There is a dual footprint for full-sized and half-sized oscillator.

Sections in more detail

Compact Flash:

This revision now has a Compact Flash socket, it is accessed in 8-bit IDE mode. There is a jumper selection on the board to allow us to select the base address of the CF from between $08 and $38 in $08 increments.

I have been working on FAT16 support for CF for the BIOS and M62-OS, so far I can read files in the root directory/folder, see here for more information on that.

ROM/RAM structure:

The ROM and RAM structure is pretty much the same as the other revisions on reset.

At reset, Bank 0 is mapped to the first page of ROM. Each page is 16K in size.

With this revision, we have a write-only memory configuration register at I/O port $00 that assigns the mapping of Bank 0.

Bit 0 selects whether we are using the ROM or the RAM, setting this bit selects the RAM while clearing it (default) selects the ROM>

Bits 1-5 configure the A14-A18 lines, which basically select which 16K page of the ROM/RAM we are using.

Note: Bank 1 is always mapped to RAM page 0 regardless of Bank 0 configuration, this is because the stack is stored at the top of bank 1 and removing access to it would cause the system to crash.

Upon reset, this register will default to $00.

This is the schematic of the Bank_0 logic. U8 (‘273) is an octal latch that holds the A14-A18 configurations for paging higher parts of the RAM/ROM. U10 (‘244) enables the A14-A18 configuration to pass through to the ROM/RAM when Bank 0 is active. When Bank 0 is not active, the outputs go high-Z and these lines have pull-down’s (not shown in this snippet) that ensure that A14-A18 are all 0’s this addressing the first page.

U7c (’00 on the left) inverts the 0x00 decoded I/O address selection to pulse the clock of U8 (‘273) loading the value from the data bus in it’s latches, thus loading the A14-18 configuration along with the bit 0 selecting whether we have ROM or RAM in Bank 0 (0=ROM, 1=RAM). This is done by issuing an OUT command to port $00 on the Z80 as described a little above.

The logic on the right size is to determine which of the ROM/RAM gets enabled based on the decoded Bank 0, Bank 1, and ROM/RAM selection. The boolean expressions and truth table are such:

!ROM_CS = !BANK_0 + ROM/RAM      !RAM_CS = (!BANK_0*!BANK_1)+!(!BANK0+ROM/RAM)

The First two selections (in red) are invalid because BANK_0 and BANK_1 are provided by U4a (not shown) which is a 74HCT139 at both of these lines should not both be active (low) at the same time.



Here is the Rev 3 all populated!

The Isolation circuitry for the UART didn’t perform as expected, so it was bypassed as seen in this photo.

The rest of the board works designed. The full 512KB of RAM is accessible and the full FlashROM (up to 512KB) is available too.

Upon testing, the CF card interface worked exactly as it did on the prototype CF interface card.

I started porting CP/M to work on here, but I have not had much time recently.