M62 Bus system – A Modular Z80 Based System

M62 Project



In progress of being updated, check regularly 🙂

Background details

The M62 Project is to develop a modular computer system that is reminiscent of computer systems from the 1980’s.

The main inspiration of this project is the IMSAI computer as seen on the videos by The IMSAI Guy on YouTube. It is also inspired in part by the Altair 8800 computer.

Project Aim

The aim of the project is to define a set of open standards for interchangeable parts that will allow the end user to reconfigure they system as they see fit.

Initial designs are based around the 8-Bit Z80 CPU but I do intend for other processors to be supported. Hopefully expanding the standard to allow for a 16-Bit, and maybe 32-Bit processors.

Designs and source code of the project will be made open source to allow others to build upon what is produced and outside input is very much welcome.

Physical Specifications

Standard Card

The previous standard card size was not fully specified, there was no actual measurements put in place to define it. There was a sub-standard called M62-Mini created quite recently but after some prototyping I have decided that this will become the new Standard Card Size

The Standard Cards are to be no larger than 10×10 cm (3937×3937 thou) to allow low cost fabrication.

Switches, connectors, indicators are to be placed on the edge opposite the edge connector, the 2 other sizes are expected to slide through card guides.

The edge connector should be approximately 500 thou from the bottom-left corner of the board.

Expanded Card

This is basically the old standard card. The only firm specification for this class of card is the position of the edge connector from the bottom-left corner (rear bottom) of the card.

Electrical Specifications

The M62 Bus is designed around the standard 5V TTL voltage levels, cards being used on this bus should conform to this otherwise damage may occur for the non-conforming card or the other cards currently on the bus.

A 12V power connection is provided and can be used for 12V devices or regulated on card to a desired voltage.

The outer most 4 connections on either size and end of the edge connector are designated for power. They consist of a 12V connection and a 5V connection interleaved with a Ground connection. They are purposefully placed symmetrically (12V, Ground, 5V, then Ground again going from outside inwards) to mitigate damage caused by card is inserted in reverse.


Data Bus

The data bus consists of 8 lines, supporting 8-bit processors and devices.

Address Bus

The address bus consists of 16 lines, allowing for addressing of 64K (65536) unique locations.

Control Bus

The control bus is based on the Z80’s control lines, if other processors are used then some logic translation may be required to generate required signals.

[ Expand details on the signals here ]

Decoded bank lines

BANK_0 -> BANK_3

These lines are decoded from the top 2 Address lines (A14 and A15) when a memory operation has been issued (the !MREQ signal being asserted). It allows the memory space to be divided into 4 banks of 16K (16384) unique locations. This can be used to simplify memory addressing or can be ignored and address decoded manually using the Address bus instead.

IO_0 -> IO_3

These lines are decoded from A6 and A7 of the Address bus when an I/O operation has been issued (the !IORQ signal being asserted). It eases the decoding of I/O locations in a similar was as the memory banks are decoded. Note: some processors do not use separate memory and I/O addressing, such as the 6502, so the IO_x lines would require some logic translation if these lines are needed.

Memory Map

The Memory Map

  • Based on a 64K memory map, I see the address space being split into 4x 16K banks,
  • Bank 0: 0x0000 to 0x3FFF – BIOS/Base ROM
  • Bank 1: 0x4000 to 0x7FFF – Base RAM
  • Bank 2: 0x8000 to 0xBFFF – Expansion Memory Bank (possibly video RAM)
  • Bank 3: 0xC000 to 0xFFFF – Expansion Memory Bank


M62 Cards

Current designs:

  • M62 Z80 SBC card : A card containing the Z80 CPU, 16K RAM, 16K FlashROM, 16C550 UART, and Memory and I/O decoding
  • M62 16-Bit IDE card : This card allows the interfaces of an IDE hard disk or a Compact flash card via an adaptor
  • Simple RAM/ROM expansion : This circuit can be implemented as a full card or be used as part of another card

Future designs:

  • M62 VGA/PS2 card : PROPOSED SPECIFICATION : This card will allow the outputting to a VGA monitor and allowing input from a PS/2 Keyboard


Additional circuits not yet fully implemented

Single stepping of the processor

In order to allow us to debug software, we need a way of single stepping the processor, this schematic uses the Z80’s M1 and Wait pins to allow us to step through. I’m still unsure if I will have this part of the circuit on the Front Panel Interface or just put it on the processor card with a cable going directly to it (as on the IMSAI) to make the front panel processor agnostic.

This circuit worked quite well when I bread-boarded the design but is not currently used on my CPU card design. It can easily be implemented into a front panel card with some display circuitry.

It’s not shown on the schematic above, but U6 is a 555 timer chip.

The breadboard is set up with LED’s on A0 and A1, and the data bus is tied to 0V to provide 0x00 (NOP instruction) regardless of what address it reads from. When the switch is in the Run position (the orange/brown wire in the middle of the breadboard being disconnected) it will run through then entire 64K memory space, “reading” NOP’s and skipping to the next address, thus making the LED’s flash as it counts up. When in the Stop position (orange/brown wire to 0v) it will allow count to the next address when the Step is toggled.

Current schematics can be found here. (This may not be fully updated yet)