Schematics can be found here.
I recently watched a bunch of videos from IMSAI Guy and really started to get all nostalgic , I had a little spare time between university semesters so I decided I should go ahead and start a fresh project. This time I wanted to make it based on a backplane, a bit like the IMSAI or ALTAIR systems, this would allow me start off very basic with each part and slowly improve and build up to something nice.
My aims for this project is as follows:
- Be modular by design
- Avoid having cards being dependants on other specific cards
- Use off the shelf parts where possible
- Have designs open source and available on this website
The initial specifications I am working on are:
- Based on the Z80 bus architecture (8-Bit data bus, 16-Bit address bus)
- 62-Pin edge connector (as used for the 8-Bit ISA slot, or XT systems)
- 5V power bus, with space for 12V power bus for future use
- 8-Bit bank address bus
- 4MHz clock
Ideas for the future:
- Using other 8-Bit processors (6502, 6800, ect..)
- Using 16-Bit (or higher?) processors, would require an expansion of the card slots (probably like the 16-Bit ISA does)
- Slave processors
- More banking support
The M62 Bus and connector
M62 Bus v1.1 pinout
The connector is the same as the ISA/XT connector (as mentioned above), I originally was going to use a 50 way connector and call it the M50 system but I found an old motherboard in my garage and found that the 62 way connectors were cheap enough on Digikey, and since they were used in a defined standard they should be more available.
Electrically it is based on the Z80 connections with an extra bank bus, as well as 12V lines.
It will also nicely fit within 10cm so I can use it on boards made using ITead studios 10cm x 10cm service ($19.90 for 10 boards, best service I’ve found so far)
Bonus trivia fact: I didn’t realise until after I settled with this connector that the main motorway (highway/freeway) near where I grew up is called the M62!
Memory and I/O Maps
The Memory Map
- Based on a 64K memory map, I see the address space being split into 4x 16K banks,
- Bank 0: 0x0000 to 0x3FFF – BIOS/Base ROM
- Bank 1: 0x4000 to 0x7FFF – Base RAM
- Bank 2: 0x8000 to 0xBFFF – Reserved for video RAM
- Bank 3: 0xC000 to 0xFFFF – Expansion Memory Bank
To be finalized
The Bank Addressing system
The top 2 address lines are used to select 1 of 4 banks for the memory, each bank is 16Kbyte in size.
The address decoding for the memory is done by one gate of a 74HCT139 Dual 2-to-4 line
decoder/demultiplexer, the other gate will be used for the I/O bank address decoding (to be finished).
Since the A14 and A15 are used for the address decoding, it leaves A0-A13 available for addressing within the banks, that is 14 address lines in total 2^14 is 16384 bytes or 16Kbytes per bank.
Single stepping of the processor
In order to allow us to debug software, we need a way of single stepping the processor, this schematic uses the Z80’s M1 and Wait pins to allow us to step through. I’m still unsure if I will have this part of the circuit on the Front Panel Interface or just put it on the processor card with a cable going directly to it (as on the IMSAI) to make the front panel processor agnostic.
This circuit worked quite well when I bread-boarded the design.
It’s not shown on the schematic above, but U6 is a 555 timer chip.
The breadboard is set up with LED’s on A0 and A1, and the data bus is tied to 0V to provide 0x00 (NOP instruction) regardless of what address it reads from. When the switch is in the Run position (the orange/brown wire in the middle of the breadboard being disconnected) it will run through then entire 64K memory space, “reading” NOP’s and skipping to the next address, thus making the LED’s flash as it counts up. When in the Stop position (orange/brown wire to 0v) it will allow count to the next address when the Step is toggled.
The single step circuitry will reside on the Z80 CPU card from now on
The current schematics are found here, these will be updated as we go along.