M62 – Modular Computer System Blog

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Schematics can be found here.

April 24 2018

I’ve been toying with some designs for computer systems the past few months, but I have been busy with university so I’ve not had much time to devote to it.

Now my exams have just finished I can put some more effort into realising a new design.

I was looking at some S-100 based systems and decided that is something I really want to create, except S-100 stuff is very expensive to get these days so I decided to devise something that doesn’t cost quite so much.

The aim for my design is to create a backplane system that I can use different processors (possibly simultaneously) and be able to use different add-on cards for extra memory, video, ect… I am initially working on a Z80 based system to begin with.

After toying with different connectors I was considering a 50 way edge connector (or 25×2 way) but having pulled an old PC motherboard out of my garage I took some of the ISA slots off (now I have a desoldering gun I can do that now), they are 62 way edge connector sockets (31×2) hence the name of the bus, coincidentally it happens to be the name of the major motorway (highway/freeway) near where I grew up.

Having looked on digikey, those connectors are not too expensive and would fit within 10cm of an edge of a board as I am using ITead studios 10cm x 10cm service.

The bus consists of all the Z80 connections as well as an 8-bit bank address bus, and 12V lines.

The Bank address bus will hold the bank address for the I/O or memory operation being performed, when using a Z80 processor write to I/O ports 0x00 and 0x01 to set the Memory bank and I/O bank addresses respectively. I’ve yet to figure out how to handle this for use with a 6502 and 6800 processors.

The Memory Map

  • Based on a 64K memory map, I see the address space being split into 4x 16K banks,
  • Bank 0: 0x0000 to 0x3FFF – Base/Boot ROM
  • Bank 1: 0x4000 to 0x7FFF – Base RAM
  • Bank 2: 0x8000 to 0xBFFF – Extended RAM/ROM or possibly part of Bank 3.
  • Bank 3: 0xC000 to 0xFFFF – Selectable Bank

I/O Map

  • Port 0x00 and 0x01 reserved for bank selects
  • 0x02-0xFF: dependent on bank selection.

April 27 2018

For the past week I have been working on constructing a prototype of the computer.

I first went about looking at creating a single step mechanism, I first through of having the clock line selectable between an oscillator running at 4MHz or a push button that I clock manually. While this will technically work, the issue with this is an instruction cycle consists of many program cycles. The solution to this is to create a circuit that uses the M1 and wait signal from the Z80 system, it uses the M1 signal to signify the fetching of an instruction and then tells the processor to wait until the step button is toggled.

The button on the left is the step button, the one on the right is the reset button.

The orange/brown wire  which is on the bottom right of the chip below the crystal is supposed to go to a switch, if it’s connected to 0V then the processor is in stop mode (or single step mode), and if it’s not connected, then it is in normal run mode and will run as normal.

This circuit worked well, so I decided to implement it in my prototype I was building.

The prototype consists of a backplane, a Z80 processor card and a front panel card.

Yes, the cards have edges glued onto them and wires jumped to them, I haven’t sent off my order to have some made yet.


This board just has 3 edge connectors, LED power indicator and a place for me to hook up some crocodile clips to power it.

Z80 processor card

This has all the pins of the CPU brought out to the edge connector, except the Reset, NMI, and INT are fed through a Schmitt trigger before they get to the processor.

Front panel card

This consists of buffers to drive LED’s that show the status of both the data bus and the address bus. The previously shown circuit is also incorporated into this card, as well as a reset button. I added headers next to the LED’s that will go to a proper front panel which I will construct out of aluminium once the switches I ordered from Ebay arrive.

I did notice afterwards that I wired up the switches and LED’s the wrong way around, the LSB is on the Left 😛 I just need to make sure I connect up the front panel switches/LED’s in the right order.

Having spent hours soldering these boards, I checked the connections with my meter. I found that 5V and 0V was shorted on the CPU card, turns out there was a small short on the copper which was badly etched (at factory, I didn’t make these boards). Once that issue was resolved, I used my scope to check the 4MHz bus and it was present as expected.

I put it all together and it worked quite well. The address and data busses are pulled down on the front panel card so the CPU read 0x00 instructions (NOP) and ran through the entire 64K address space continuously, I put it in stop mode (single step mode) and it steps through each NOP and I was able to see the address bus counting up in binary with every toggle.

This is technically this computer running “code” for the first time, sure all the code consists of NOP instructions but it is executing.

Next step is to add Examine/Deposit functions to the front panel card and build a memory card and attempt to run a stored program.

April 28 2018

I added a switch and LED to allow me to request the bus from the processor and get a response, this works great, I then put on the Examine and Deposit buttons on according to the circuit below, but I need a memory card to test this.

I started building a new card to turn into the memory card, I had to salvage another edge piece off another board, but this has some fingers missing so I had to peel off some copper traces from the donor board and glue them onto the edge.

This will eventually be the memory card, I just have to decide on how I am decoding the addresses on it.

I did another command test on the computer as a whole, I set the data switches on the front panel to 0xFF and stepped the CPU, according to the datasheet, 0xFF is RST38. When I clocked the CPU, all the address bus lines went high, then on the next clock it was 0x0039. which shows me that it actually followed the command, this is very much promising and I can’t wait until I can start running code from memory on this computer.

May 1 2018

The diode method previously mentioned to put the examine/deposit buttons onto the system did not work, even after buffering it. I believe it is a timing issue or the bad connectivity of the recycles edge sockets, I have some fresh ones just in from Digikey and I am waiting for my PCB’s to be made, unfortunately there is some kind of Chinese holiday which will delay things, I will eventually get some videos done and hopefully a better webpage made up for this project soon, just started my spring semester at university which is only Mon-Wed, so I should have spare time to work on this.


May 4 2018

ITead studies emailed me this morning letting me know that they are now proceeding with the manufacturing of my boards, I can’t wait for those to come in.

Here is a couple of 3D renderings from DesignSpark, the left board is the backplane adaptor, the right one is a set of 4 bus adaptors.

For the bus adaptors, you cut them out and attach them to a prototyping board (same as what I did with the edge connectors, but this is cleaner) and the connections are all available and labelled for ease of use.

Today I was working on my front panel card, memory card, and a debugging card.

Front Panel Card

The front panel card was modified, I flipped the address and data wiring so the LSB is now on the right for both busses on the switches and LED’s.

I removed the old Examine/Deposit circuitry and reused the buttons to do RD/WR lines, and use the spare switch next to BUSREQ for MREQ, this now allows me to read and write to memory on the system manually.

Memory Card

The large chip is a Fujitsu MB84256C 32KByte RAM, I put the tape on top so I could write down the pins I wanted to check while I was debugging the front panel and proving the address decoding circuit.

The board only had the RAM on it, but I am still deciding if I want a ROM on it too, or just another RAM which will be bootloaded by the debugging card.

Debugging card

The debugging card is basically a card with a socket for an Arduino Mega on it wired up to all the busses.

The space to the right of the Arduino is intended for a SD socket module, this will allow me to write binary files from my laptop and put them on a SD card and put them into the system, and I plan to have the Arduino hold the processor in reset, copy the binary file to RAM in the ROM area, then allow the system to boot as normal.

I currently have the Arduino writing to the RAM and reading it back to check that the RAM is addressing correctly. Next I will write routines that allows me to input bytes into the memory by typing them into through the Arduino’s serial terminal.

May 5 2018

I have added a ROM to the RAM card and put jumpers on it so I can select if the ROM or RAM is at either 0x0000 or 0x4000

I also did some work on the Arduino code and was able to have it read and write the memory on this card.

The RAM can be read/written using the switches on the front panel now, which is what is wanted. I was able to write a small 6 byte program that just tells the cpu to jump to address 0x200, at 0x200 I had the instruction to jump to 0x0000, so it loops around. I put the system in bus request mode, then used the switches to load the program into the RAM (which was selected to be at 0x0000) then I released the bus and stepped the CPU through the program and it worked as it was supposed to! I will try and get a video of this tomorrow.

The FlashROM I used turns out to have some Z80 code on it from one of my other projects, and the processor runs it when it’s selected to be at 0x0000, though I have not checked what it was supposed to be doing.

I can’t wait for my switches to arrive from Ebay, it’s very tedious using those little tiny dip switches with my tweezers.

May 11 2018

I’ve not managed to get any new videos done, but I have done some more testing with the Arduino interface as well as the DIP switches. I added an NMI button on the front panel card and have made a short piece of code to write 0x4D (M in ASCII) to the first position of RAM (0x4000 in this case) and then loop forever at the same address, and at the NMI vector (0x0066) I have the code writing 0x4D to 2nd RAM position (0x4001). The code seems to work well, I had to make sure the stack pointer was all set up before NMI would work correctly, but now when I run the processor, I can put the system in BUSREQ mode and use the front panel to look at address 0x4000 and I see 0x4D is there, and 0x4001 is not 0x4D (sometimes RAM has random bytes when not initialised), I release the BUSREQ and press my NMI button and put it back in BUSREQ mode, and I can see that both 0x4000 and 0x4001 now contain 0x4D, this shows that the system is correctly running from FlashROM, writing to RAM, and handling the NMI properly.

The next part to test is the bank addressing section, I don’t have any octal latches at hand so I will have to order some when I do my next digikey order, I appear to be short of a few logic chips 😛

Beyond this, I can’t really do too much more experimenting until my boards come back from the fab house, they are currently in transit from China 🙂 I only have 3 slots in my protoype system and I’m keeping the 4 new sockets until the boards come in, (going to desolder the sockets from the prototype and put the on a board too when they come in, then I can have 7 slots).

Future plans

I want to put the front panel interface on a card that plugs into one the 62-pin headers that were designed for expanding the backplane board. Since this is considered as a somewhat permanent part of the system, then I wanted to free up the slots for the removable cards.

Moving the stepping circuitry to the processor card, as well as the banking circuitry once I get it tested, will be a good idea.

Physical considerations

I’ve been thinking about how I would create a frame for this board to create a nice stable casing for everything

Originally I was going with the idea of the cards being shaped as they are on the left, but I’m not thinking of the connector being on the end of the board and having the board as a standard height (like the one on the right) so I can make slides for the cards to go into to guide it into the connector, similar to the system used by Bernd Ulmann (except mine uses edge connectors)

I will fashion a frame out of some aluminium when my rivets arrive (ordered from eBay) and eventually I will 3D print some guides once the Makerspace at the University is back up and running.

My email is peter@39k.ca


Having received feedback and thought a little more, I will be sticking with the orientation of the boards (the left one in the image above) as it keeps it simpler and allows me to eventually add an expansion for the bus, also it allows me to put more connections on the top. I will still put slides either side of the card, they will just be further spaced.

I have just set up a sub-page showing you how to set up a Z80 assember and a freeware hex editor to work with programmer’s notepad. These instructions only work with Windows as far as I know, if you have a solution for Mac you would like to suggest, I would love to hear.

Setting up Assembler and Hex editor

I have also done some research on the I/O structure of the Z80 and will be putting up some more information soon. It will modify what I have in mind for the banking system, and may change the memory map slightly (at least just the top 2 banks).

May 25 2018 (very early AM)

I decided to design a card guide for 3D printing since I heard that the University Makerspace was opening for a few hours each day during the Spring/Summer.

This is a mock up of what it will look like, I did this in TinkerCAD.

I managed to get into the Makerspace at the University yesterday and print a pair off. 2 hours later (actually 1 hour and 42 mins) they were finished. Unfortunately they came out somewhat warped 😛 Also the pictures above doesn’t have the support material removed, I should have printed a raft, maybe that would have prevented the warp, I’ll try again Tuesday.

After cleaning off the support material and using a lighter to heat the plastic, I managed to bend it somewhat straight.

Here are the guides in all their glory.

The guides are designed to be bolted to the case, keeping them physically independent from the backplane PCB.

As soon as the backplane PCB’s arrive I will move on to creating a case for it, then I can really get into the prototyping.

As for circuit development, I am working on trying to create a plan of action for the newer banking control, I was thinking of having 2 sets of 8-bit latches, for bank 2 and 3. so when bits 14 and 15 select either bank 2 or 3, then the contents of the relevant bank will be present on the Bank Address bus. For testing I will start with just a single latch set then expand it when it’s proven.

May 27 2018

After a bad night of migraines I managed to implement the bank controlling circuitry. I put it on the memory card for now as it had room for it, while the CPU card did not. I will be making another set of cards (CPU and Memory) when my edge breakouts and the backplane boards finally come in, so I will be implementing all the new revised circuits. The single stepping, power on reset, and bank controlling circuit will reside on the CPU card.

This is the new memory map I will be working with from now on.

Bank 0 will be the main 16K of ROM, bank 1 will be the main 16K of RAM

Banks 2 and 3 will also be 16K in size, but will be able to select 256K sub-banks

Note: The map is mainly a guide, the actually address decoding will be performed on the separate memory cards themselves, I know some computers have a dedicated decoder circuit, but I found that if each memory card has it’s own circuit then it can be flexible on how it is mapped.


I currently have the Bank 2 register wired up, it’s is trivial to wire up the Bank 3 register but I just wanted to get at least one working to prove the circuit.

When I do an I/O write to 0x0000 it will set the value of the data bus into the latches of the Bank 2 register, and when select a memory address between 0x8000 and 0xBFFF (inclusive), the contents of the Bank 2 register will be present of the Bank address bus (BA0-BA7).

Doing an I/O write to 0x0001 will do the exact same thing for the Bank 3 register (this will need to be confirmed when it’s wired up), selecting memory addresses between 0xC000 and 0xFFFF (inclusive) will present the Bank 3 register contents as above.

I used a pair of PLDs to do the address decoding, I write the code in a way so the same code would go into both PLDs, I ended up using all the pins on the PLDs and didn’t have enough to include the !WR line, so whether you do an I/O Read or Write (IN/OUT) to 0x0000 or 0x0001, it will change the respective register, basically if you read the I/O port for the register it will zero it out. I should re-write the PLD code so I have an upper and lower version, this will free up a couple of pins so I can use the !WR to correct for this, but for now it is fine.

The current Z80 CPU card schematic that shows the equivalent circuitry of the PLD can be found here


An extension was added onto the front panel card to allow me to display the bank address bus, the !IORQ line as well as add a jumper to activate the !IORQ line (this board is going to be replaced so I didn’t want to waste a switch on it). (Picture will be added soon, I mounted the pair of slides to see what it would be like too)


In other news, I managed to confirm that we can indeed use the full 16-bit address bus with I/O operations. This is something that is documented in the datasheet and I have often wondered why it’s not used much. As far as I know, almost all manufacturers of add-ons for the popular Z80 based computers ignore the top half of the address bus, this let me (and many others) to believe that you can only use 8-bit addressing, but I now think that the top half was ignored by manufacturers of add-ons as to save money on extra address decoding circuitry, and the cost of memory and I/O devices in those days meant that very few people would have the need to address more than 256 ports of I/O anyway.

more info and pictures to come soon.

June 4 2018

Major revisions have been made.

You can find the current schematics here.

Due to restructuring I have updated the current card schematics. The banking system has been redesigned

Here is the current memory map:

As you can see, it’s not much different from previous. This is also the same as the I/O map.

I have made an 82C55A I/O Card, you can find the schematics in the link above.

I’m having issues with RET instruction not being obeyed by the Z80 and working through the issue, I’ve ruled out the CPU itself, the RAM, address decoding as well as the backplane. My designed boards should be coming in soon so I can start to re-build the cards and hopefully iron this bug out.

I will have more updates soon.

July 29 2018

It’s been nearly 2 months since I did an update, I have however recently posted a new video as there has been a huge amount of progress that has been made.

To sum it up, I’ve made a few decisions for the design and have implemented them with great success.

The RET bug now appears to be resolved, it was most likely the combination of some bad soldering joints and the mixing of different variants of 74 TTL logic, I now have all HCT variants which seems to be fine.

The Memory bank layout is pretty much the same as before, and I’ve reverted back to 8-Bit addressing for the I/O as it makes more sense at the moment. This is something that could be expanded later on.

I’ve designated banks of the memory for functions as follows:

  • Bank 0 : BIOS/Main ROM
  • Bank 1 : Main RAM
  • Bank 2 : Video RAM*
  • Bank 3 : Expansion ROM/RAM

*Reserved for when I get a video card designed and developed.

The BIOS will be a collection of assembled routines which can be called using their addresses, this will save having to write these routines again thus saving time and space. I have created a java app to parse the .LST file that TASM generates when it assembles a file. I just run the parser on the output from the BIOS assembly and that will generate a file that holds the entry addresses of all the routines contained within the BIOS so they can be used.

The parser .JAR file can be found here: http://39k.ca/m62/parser.jar

To use the parser, you can just run it and it will prompt for the input file and output file, but you can include these files via the command line.

java -jar <input filename> <output filename>

The output may need a little aligning of the tabs, it’s purely a cosmetic issue that I hope to fix eventually.

I now have an expanded memory interface card that will logically support up to 10 chips (I only have 2 sockets on the board for now) and the limit of each of those chips is 32MBit (or 4Mbyte), theoretically you can have 40MBytes of memory on this card. There is a register that holds the expanded address lines A14-A21 to allow access to the memory beyond the 16Kbyte window provided by the bank. The base address of the I/O is set by jumpers but the memory is hard wired to be in Bank 3 (0xC000 – 0xFFFF), The 16Kbyte window is moved by using 3 I/O ports:

  • base : writing anything to this port will increment the select, it will wrap around back to 1 after 10.
  • base+1 : writing anything to this port will reset the select back to chip 1
  • base+2 : writing a byte to this port will load the expanded address register with that byte.

In this picture I have a pair of 128Kbyte NVRAM’s, there is a lot of unused parts on this board as I have modified the circuit a lot to get it to work. The green LED’s show which of the 10 chips are selected, and the red LED’s show the contents of the expanded address register.

There should be a video demonstrating it being made soon.

As for the software side of things, I found a monitor made by Matt Cook that I have expanded with the help of Zeddy, my patreon, together we have made it into something that is very useful but I wish to take the system further by implementing the BIOS system as mentioned before. This will also include a menu system that will scan the expanded memory for executable blocks (they will have a specific signature in a header to allow it to be detected). This is currently in the early planning stage.

I will be updating the schematics here shortly.

bye for now

August 16 2018

I rebuilt the RAM/ROM expansion card and tinkered with the design a little. It will now allow you to read back the extended address from the same port you wrote it to. Maybe in the next revision I will include a way to read back the position on the chip selection.

The schematics for this board has been updated to version 1.1 and is now available here.

(Note: the schematic shows all 10 chip sockets and jumper configurations for each socket, the card shown was wired specifically for these 32Kbyte RAM’s)

As you can see, there is a lot of wiring in this board. It took ~10 hours spaced over 3 days as I checked pretty much every connection with the meter. When I come to test it, I found that everything would work as long as I didn’t have a chip in socket 0. After some good head scratching and lots of tracing wires it turned out that there was a whisker of wire that I failed to trim from the wiring under the chip select connection under socket 0 that was touching GND, this was enabling the chip in that socket causing contention.